30 #define QQQdialect MPLABX 44 #undef QQQMULTIPROCESSEXH 47 #define qqqMaxBranchDepth 20 48 #define QQQstructbitmap 60 #undef QQQTEMPLATEONLY 62 #define QQQUPLOADATEND 64 #undef QQQASHLINGVITRA 66 #define qqqbitmapint unsigned int 68 #undef QQQTIC2XSERIALIO 70 #undef QQQCOMPRESSED_EXH 77 #define fsk_60zzopen zzopen 79 #define fsk_60zqqzqz1 zqqzqz1 82 #define FILEPOINT FILE * f, 83 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 112 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 113 #ifndef LDRA_VOID_FUNC 114 #define LDRA_VOID_FUNC 117 #if defined(QQQMAINFL) 140 #ifdef QQQ_KEEPCOMMENTS 148 #if !defined(QQQSUPPRESS_UNDEF) 154 #undef QQQHITMAP_STORAGE 156 #define qqnull_params void 157 #define QQQ_PROTOTYPE_DEF 159 #undef QQ_ANSI_PROTOTYPE 161 #define QQ_ANSI_PROTOTYPE 1 164 #define QQ_ANSI_PROTOTYPE 1 170 #define ELEMENT(N) qqqbitmapint element##N; 172 #include "fsk_60zbelem.def" 176 #define ELEMENT(N) 0, 178 #include "fsk_60zbelem.def" 255 #ifndef _SYSTEM_CONFIG_H 256 #define _SYSTEM_CONFIG_H 275 #define SYS_VERSION_STR "2.06" 276 #define SYS_VERSION 20600 280 #define SYS_CLK_FREQ 200000000ul 281 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 282 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 283 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 284 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 285 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 286 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 287 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 288 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 289 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 291 #define SYS_PORT_A_ANSEL 0x3F00 292 #define SYS_PORT_A_TRIS 0xFFED 293 #define SYS_PORT_A_LAT 0x0010 294 #define SYS_PORT_A_ODC 0x0000 295 #define SYS_PORT_A_CNPU 0x0020 296 #define SYS_PORT_A_CNPD 0x0000 297 #define SYS_PORT_A_CNEN 0x0021 298 #define SYS_PORT_B_ANSEL 0x10C8 299 #define SYS_PORT_B_TRIS 0x91FF 300 #define SYS_PORT_B_LAT 0x0000 301 #define SYS_PORT_B_ODC 0x0000 302 #define SYS_PORT_B_CNPU 0x0000 303 #define SYS_PORT_B_CNPD 0x0000 304 #define SYS_PORT_B_CNEN 0x0000 305 #define SYS_PORT_C_ANSEL 0xCFE1 306 #define SYS_PORT_C_TRIS 0xFFFF 307 #define SYS_PORT_C_LAT 0x0000 308 #define SYS_PORT_C_ODC 0x0000 309 #define SYS_PORT_C_CNPU 0x0000 310 #define SYS_PORT_C_CNPD 0x0000 311 #define SYS_PORT_C_CNEN 0x0000 312 #define SYS_PORT_D_ANSEL 0xC100 313 #define SYS_PORT_D_TRIS 0xFFFF 314 #define SYS_PORT_D_LAT 0x0000 315 #define SYS_PORT_D_ODC 0x0000 316 #define SYS_PORT_D_CNPU 0x0000 317 #define SYS_PORT_D_CNPD 0x0000 318 #define SYS_PORT_D_CNEN 0x0000 319 #define SYS_PORT_E_ANSEL 0xFC00 320 #define SYS_PORT_E_TRIS 0xFDFF 321 #define SYS_PORT_E_LAT 0x0000 322 #define SYS_PORT_E_ODC 0x0000 323 #define SYS_PORT_E_CNPU 0x0000 324 #define SYS_PORT_E_CNPD 0x0000 325 #define SYS_PORT_E_CNEN 0x0000 326 #define SYS_PORT_F_ANSEL 0xCEC0 327 #define SYS_PORT_F_TRIS 0xEFFF 328 #define SYS_PORT_F_LAT 0x0000 329 #define SYS_PORT_F_ODC 0x0000 330 #define SYS_PORT_F_CNPU 0x0000 331 #define SYS_PORT_F_CNPD 0x0000 332 #define SYS_PORT_F_CNEN 0x0000 333 #define SYS_PORT_G_ANSEL 0x8CBC 334 #define SYS_PORT_G_TRIS 0xDFFF 335 #define SYS_PORT_G_LAT 0x0000 336 #define SYS_PORT_G_ODC 0x0000 337 #define SYS_PORT_G_CNPU 0x0000 338 #define SYS_PORT_G_CNPD 0x0000 339 #define SYS_PORT_G_CNEN 0x0000 340 #define SYS_PORT_H_ANSEL 0x0070 341 #define SYS_PORT_H_TRIS 0xB3FB 342 #define SYS_PORT_H_LAT 0x0000 343 #define SYS_PORT_H_ODC 0x0000 344 #define SYS_PORT_H_CNPU 0x0000 345 #define SYS_PORT_H_CNPD 0x0000 346 #define SYS_PORT_H_CNEN 0x0000 347 #define SYS_PORT_J_ANSEL 0x0000 348 #define SYS_PORT_J_TRIS 0x8B7F 349 #define SYS_PORT_J_LAT 0x0080 350 #define SYS_PORT_J_ODC 0x0000 351 #define SYS_PORT_J_CNPU 0x0000 352 #define SYS_PORT_J_CNPD 0x0000 353 #define SYS_PORT_J_CNEN 0x0800 354 #define SYS_PORT_K_ANSEL 0xFF00 355 #define SYS_PORT_K_TRIS 0xFFFF 356 #define SYS_PORT_K_LAT 0x0000 357 #define SYS_PORT_K_ODC 0x0000 358 #define SYS_PORT_K_CNPU 0x0000 359 #define SYS_PORT_K_CNPD 0x0000 360 #define SYS_PORT_K_CNEN 0x0000 364 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 365 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 366 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 367 #define SYS_TMR_FREQUENCY 1000 368 #define SYS_TMR_FREQUENCY_TOLERANCE 10 369 #define SYS_TMR_UNIT_RESOLUTION 10000 370 #define SYS_TMR_CLIENT_TOLERANCE 10 371 #define SYS_TMR_INTERRUPT_NOTIFICATION false 377 #define DRV_IC_DRIVER_MODE_STATIC 380 #define DRV_SPI_NUMBER_OF_MODULES 6 383 #define DRV_SPI_POLLED 1 384 #define DRV_SPI_ISR 0 385 #define DRV_SPI_MASTER 1 386 #define DRV_SPI_SLAVE 0 388 #define DRV_SPI_EBM 1 389 #define DRV_SPI_8BIT 1 390 #define DRV_SPI_16BIT 1 391 #define DRV_SPI_32BIT 0 392 #define DRV_SPI_DMA 0 394 #define DRV_SPI_INSTANCES_NUMBER 3 395 #define DRV_SPI_CLIENTS_NUMBER 3 396 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 398 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 399 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 400 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 401 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 402 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 403 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 404 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 405 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 406 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 407 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 408 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 409 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 410 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 411 #define DRV_SPI_BAUD_RATE_IDX0 1000000 412 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 413 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 414 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 415 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 416 #define DRV_SPI_QUEUE_SIZE_IDX0 10 417 #define DRV_SPI_RESERVED_JOB_IDX0 1 419 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 420 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 421 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 422 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 423 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 424 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 425 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 426 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 427 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 428 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 429 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 430 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 431 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 432 #define DRV_SPI_BAUD_RATE_IDX1 1000000 433 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 434 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 435 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 436 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 437 #define DRV_SPI_QUEUE_SIZE_IDX1 10 438 #define DRV_SPI_RESERVED_JOB_IDX1 1 440 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 441 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 442 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 443 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 444 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 445 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 446 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 447 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 448 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 449 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 450 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 451 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 452 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 453 #define DRV_SPI_BAUD_RATE_IDX2 500000 454 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 455 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 456 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 457 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 458 #define DRV_SPI_QUEUE_SIZE_IDX2 10 459 #define DRV_SPI_RESERVED_JOB_IDX2 1 461 #define DRV_TMR_INTERRUPT_MODE true 463 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 464 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 465 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 466 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 467 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 468 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 469 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 470 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 471 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 472 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 473 #define DRV_TMR_POWER_STATE_IDX0 474 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 475 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 476 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 477 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 478 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 479 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 480 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 481 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 482 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 483 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 484 #define DRV_TMR_POWER_STATE_IDX1 486 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 487 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 488 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 489 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 490 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 491 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 492 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 493 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 494 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 495 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 496 #define DRV_TMR_POWER_STATE_IDX2 498 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 499 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 500 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 501 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 502 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 503 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 504 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 505 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 506 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 507 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 508 #define DRV_TMR_POWER_STATE_IDX3 510 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 511 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 512 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 513 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 514 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 515 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 516 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 517 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 518 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 519 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 520 #define DRV_TMR_POWER_STATE_IDX4 524 #define DRV_USART_INSTANCES_NUMBER 1 525 #define DRV_USART_CLIENTS_NUMBER 1 526 #define DRV_USART_INTERRUPT_MODE false 527 #define DRV_USART_BYTE_MODEL_SUPPORT true 528 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 529 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 537 #define DRV_USBHS_DEVICE_SUPPORT true 539 #define DRV_USBHS_HOST_SUPPORT false 541 #define DRV_USBHS_INSTANCES_NUMBER 1 543 #define DRV_USBHS_INTERRUPT_MODE true 545 #define DRV_USBHS_ENDPOINTS_NUMBER 2 548 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 550 #define USB_DEVICE_INSTANCES_NUMBER 1 552 #define USB_DEVICE_EP0_BUFFER_SIZE 64 554 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 562 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 563 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 564 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 565 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 566 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 568 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 569 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 570 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 571 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 572 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 574 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 575 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 576 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 577 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 578 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 580 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 581 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 582 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 583 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 584 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 586 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 587 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 588 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 589 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 590 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 592 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 593 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 594 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 595 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 596 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 598 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 599 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 600 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 601 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 602 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 604 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 605 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 606 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 607 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 608 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 610 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 611 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 612 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 613 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 614 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 616 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 617 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 618 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 619 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 620 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 622 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 623 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 624 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 625 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 626 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 628 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 629 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 630 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 631 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 632 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 634 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 635 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 636 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 637 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 638 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 640 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 641 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 642 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 643 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 644 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 646 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 647 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 648 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 649 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 650 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 652 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 653 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 654 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 655 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 656 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 658 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 659 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 660 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 661 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 662 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 664 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 665 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 666 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 667 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 668 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 670 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 671 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 672 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 673 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 674 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 676 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 678 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 680 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 682 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 684 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 686 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 688 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 690 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 692 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 694 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 696 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 698 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 700 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 702 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 704 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 706 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 708 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 709 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 710 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 711 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 712 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 713 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 714 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 757 #ifndef _SYS_DEFINITIONS_H 758 #define _SYS_DEFINITIONS_H 767 #include "system/common/sys_common.h" 768 #include "system/common/sys_module.h" 813 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 852 #ifndef _DRV_COMMON_H 853 #define _DRV_COMMON_H 955 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 965 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 975 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1031 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1042 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1057 #define _PLIB_UNSUPPORTED 1065 #include "system/common/sys_module.h" 1077 #define DRV_IC_INDEX_0 0 1078 #define DRV_IC_INDEX_1 1 1079 #define DRV_IC_INDEX_2 2 1080 #define DRV_IC_INDEX_3 3 1081 #define DRV_IC_INDEX_4 4 1082 #define DRV_IC_INDEX_5 5 1083 #define DRV_IC_INDEX_6 6 1084 #define DRV_IC_INDEX_7 7 1085 #define DRV_IC_INDEX_8 8 1086 #define DRV_IC_INDEX_9 9 1087 #define DRV_IC_INDEX_10 10 1088 #define DRV_IC_INDEX_11 11 1089 #define DRV_IC_INDEX_12 12 1090 #define DRV_IC_INDEX_13 13 1091 #define DRV_IC_INDEX_14 14 1092 #define DRV_IC_INDEX_15 15 1124 const SYS_MODULE_INDEX index ,
1125 const SYS_MODULE_INIT *
const init ) ;
1147 const SYS_MODULE_INDEX drvIndex ,
1192 const SYS_MODULE_INDEX drvIndex ,
1325 #ifndef _DRV_IC_STATIC_H 1326 #define _DRV_IC_STATIC_H 1327 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1328 #define DRV_IC_Close( handle ) 1367 #include "system/devcon/sys_devcon.h" 1368 #include "system/clk/sys_clk.h" 1369 #include "system/int/sys_int.h" 1370 #include "system/tmr/sys_tmr.h" 1412 #ifndef _DRV_ADC_STATIC_H 1413 #define _DRV_ADC_STATIC_H 1414 #include <stdbool.h> 1415 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1416 #include "peripheral/adchs/plib_adchs.h" 1417 #include "peripheral/int/plib_int.h" 1457 uint8_t bufIndex ) ;
1461 uint8_t bufIndex ) ;
1511 #ifndef _DRV_TMR_STATIC_H 1512 #define _DRV_TMR_STATIC_H 1561 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1562 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1563 #include "peripheral/tmr/plib_tmr.h" 1599 #ifndef _TMR_DEFINITIONS_PIC32M_H 1600 #define _TMR_DEFINITIONS_PIC32M_H 1658 #include "system/int/sys_int.h" 1659 #include "system/clk/sys_clk.h" 1678 #define DRV_TMR_INDEX_0 0 1679 #define DRV_TMR_INDEX_1 1 1680 #define DRV_TMR_INDEX_2 2 1681 #define DRV_TMR_INDEX_3 3 1682 #define DRV_TMR_INDEX_4 4 1683 #define DRV_TMR_INDEX_5 5 1684 #define DRV_TMR_INDEX_6 6 1685 #define DRV_TMR_INDEX_7 7 1686 #define DRV_TMR_INDEX_8 8 1687 #define DRV_TMR_INDEX_9 9 1688 #define DRV_TMR_INDEX_10 10 1689 #define DRV_TMR_INDEX_11 11 1700 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1785 uint32_t dividerMin ;
1787 uint32_t dividerMax ;
1790 uint32_t dividerStep ;
1806 SYS_MODULE_INIT moduleInit ;
1808 TMR_MODULE_ID tmrId ;
1812 TMR_PRESCALE prescale ;
1816 INT_SOURCE interruptSource ;
1824 bool asyncWriteEnable ;
1839 uint32_t alarmCount ) ;
1901 const SYS_MODULE_INDEX drvIndex ,
1902 const SYS_MODULE_INIT *
const init ) ;
1942 SYS_MODULE_OBJ
object ) ;
1989 SYS_MODULE_OBJ
object ) ;
2023 SYS_MODULE_OBJ
object ) ;
2077 const SYS_MODULE_INDEX index ,
2178 uint32_t counterPeriod ) ;
2668 TMR_PRESCALE preScale ) ;
2908 #ifndef _DRV_TMR_DEPRECATED_H 2909 #define _DRV_TMR_DEPRECATED_H 2950 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3014 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3079 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3138 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3199 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3258 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3319 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3349 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3381 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3412 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3444 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3506 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3571 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3588 #include "peripheral/tmr/plib_tmr.h" 3589 #include "peripheral/int/plib_int.h" 3591 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3593 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3595 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3597 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3616 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3622 static inline SYS_STATUS
3625 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3636 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3647 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3657 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3666 TMR_PRESCALE prescale ) ;
3697 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3726 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3732 static inline SYS_STATUS
3735 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3746 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3757 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3767 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3776 TMR_PRESCALE prescale ) ;
3807 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3836 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3842 static inline SYS_STATUS
3845 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3856 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3867 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3877 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3886 TMR_PRESCALE prescale ) ;
3917 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3946 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3952 static inline SYS_STATUS
3955 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3966 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3977 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3987 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3996 TMR_PRESCALE prescale ) ;
4027 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4056 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4062 static inline SYS_STATUS
4065 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4076 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4087 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4097 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4106 TMR_PRESCALE prescale ) ;
4137 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4156 #include "peripheral/int/plib_int.h" 4198 #ifndef _DRV_PMP_STATIC_H 4199 #define _DRV_PMP_STATIC_H 4200 #include "peripheral/pmp/plib_pmp.h" 4215 PMP_DATA_WAIT_STATES dataWait ,
4216 PMP_STROBE_WAIT_STATES strobeWait ,
4217 PMP_DATA_HOLD_STATES dataHold ) ;
4272 #ifndef _DRV_USART_STATIC_H 4273 #define _DRV_USART_STATIC_H 4312 #ifndef _DRV_USART_STATIC_LOCAL_H 4313 #define _DRV_USART_STATIC_LOCAL_H 4320 #include <stdbool.h> 4357 #ifndef _DRV_USART_H 4358 #define _DRV_USART_H 4398 #ifndef _DRV_USART_DEFINITIONS_H 4399 #define _DRV_USART_DEFINITIONS_H 4405 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4406 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4443 #ifndef _PLIB_USART_H 4444 #define _PLIB_USART_H 4487 #ifndef _USART_PROCESSOR_H 4488 #define _USART_PROCESSOR_H 4497 #include <stdbool.h> 4498 #error "No Processor Family specified" 4542 USART_MODULE_ID index ) ;
4572 USART_MODULE_ID index ) ;
4604 USART_MODULE_ID index ) ;
4638 USART_MODULE_ID index ,
4639 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4668 USART_BRG_CLOCK_SOURCE
4670 USART_MODULE_ID index ) ;
4724 USART_MODULE_ID index ) ;
4754 USART_MODULE_ID index ) ;
4783 USART_MODULE_ID index ) ;
4815 USART_MODULE_ID index ) ;
4846 USART_MODULE_ID index ) ;
4888 USART_MODULE_ID index ) ;
4921 USART_MODULE_ID index ) ;
4953 USART_MODULE_ID index ) ;
4994 USART_MODULE_ID index ,
4995 uint32_t clockFrequency ,
4996 uint32_t baudRate ) ;
5037 USART_MODULE_ID index ,
5038 uint32_t clockFrequency ,
5039 uint32_t baudRate ) ;
5072 USART_MODULE_ID index ,
5073 int32_t clockFrequency ) ;
5108 USART_MODULE_ID index ,
5143 USART_MODULE_ID index ) ;
5178 USART_MODULE_ID index ,
5213 USART_MODULE_ID index ) ;
5245 USART_MODULE_ID index ) ;
5279 USART_MODULE_ID index ) ;
5312 USART_MODULE_ID index ) ;
5345 USART_MODULE_ID index ) ;
5379 USART_MODULE_ID index ,
5424 USART_MODULE_ID index ) ;
5458 USART_MODULE_ID index ) ;
5494 USART_MODULE_ID index ) ;
5531 USART_MODULE_ID index ,
5571 USART_MODULE_ID index ) ;
5609 USART_MODULE_ID index ) ;
5644 USART_MODULE_ID index ) ;
5678 USART_MODULE_ID index ) ;
5712 USART_MODULE_ID index ) ;
5745 USART_MODULE_ID index ) ;
5777 USART_MODULE_ID index ) ;
5809 USART_MODULE_ID index ) ;
5842 USART_MODULE_ID index ) ;
5876 USART_MODULE_ID index ) ;
5905 USART_MODULE_ID index ) ;
5934 USART_MODULE_ID index ) ;
5966 USART_MODULE_ID index ) ;
5998 USART_MODULE_ID index ) ;
6028 USART_MODULE_ID index ) ;
6058 USART_MODULE_ID index ) ;
6087 USART_MODULE_ID index ) ;
6116 USART_MODULE_ID index ) ;
6150 USART_MODULE_ID index ,
6151 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6183 USART_MODULE_ID index ,
6184 USART_RECEIVE_INTR_MODE interruptMode ) ;
6217 USART_MODULE_ID index ,
6218 USART_LINECONTROL_MODE dataFlowConfig ) ;
6251 USART_MODULE_ID index ,
6252 USART_HANDSHAKE_MODE handshakeConfig ) ;
6285 USART_MODULE_ID index ,
6316 USART_MODULE_ID index ) ;
6345 USART_MODULE_ID index ) ;
6376 USART_MODULE_ID index ) ;
6407 USART_MODULE_ID index ) ;
6437 USART_MODULE_ID index ) ;
6469 USART_MODULE_ID index ,
6470 USART_OPERATION_MODE operationmode ) ;
6500 USART_MODULE_ID index ) ;
6533 USART_MODULE_ID index ) ;
6562 USART_MODULE_ID index ) ;
6592 USART_MODULE_ID index ) ;
6628 USART_MODULE_ID index ) ;
6679 USART_MODULE_ID index ,
6682 bool wakeFromSleep ,
6727 USART_MODULE_ID index ,
6728 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6729 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6730 USART_OPERATION_MODE operationMode ) ;
6776 USART_MODULE_ID index ,
6777 uint32_t systemClock ,
6823 USART_MODULE_ID index ) ;
6844 USART_MODULE_ID index ) ;
6865 USART_MODULE_ID index ) ;
6899 USART_MODULE_ID index ) ;
6926 USART_MODULE_ID index ) ;
6952 USART_MODULE_ID index ) ;
6979 USART_MODULE_ID index ) ;
7005 USART_MODULE_ID index ) ;
7030 USART_MODULE_ID index ) ;
7056 USART_MODULE_ID index ) ;
7081 USART_MODULE_ID index ) ;
7107 USART_MODULE_ID index ) ;
7132 USART_MODULE_ID index ) ;
7158 USART_MODULE_ID index ) ;
7185 USART_MODULE_ID index ) ;
7211 USART_MODULE_ID index ) ;
7237 USART_MODULE_ID index ) ;
7264 USART_MODULE_ID index ) ;
7291 USART_MODULE_ID index ) ;
7318 USART_MODULE_ID index ) ;
7344 USART_MODULE_ID index ) ;
7369 USART_MODULE_ID index ) ;
7395 USART_MODULE_ID index ) ;
7422 USART_MODULE_ID index ) ;
7448 USART_MODULE_ID index ) ;
7474 USART_MODULE_ID index ) ;
7499 USART_MODULE_ID index ) ;
7524 USART_MODULE_ID index ) ;
7549 USART_MODULE_ID index ) ;
7575 USART_MODULE_ID index ) ;
7600 USART_MODULE_ID index ) ;
7626 USART_MODULE_ID index ) ;
7652 USART_MODULE_ID index ) ;
7677 USART_MODULE_ID index ) ;
7703 USART_MODULE_ID index ) ;
7728 USART_MODULE_ID index ) ;
7753 USART_MODULE_ID index ) ;
7780 USART_MODULE_ID index ) ;
7805 USART_MODULE_ID index ) ;
7831 USART_MODULE_ID index ) ;
7896 #include "system/common/sys_common.h" 7897 #include "system/common/sys_module.h" 7909 #include "system/int/sys_int.h" 7981 #ifndef _SYS_DMA_DEFINITIONS_H 7982 #define _SYS_DMA_DEFINITIONS_H 7988 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7989 #include "system/common/sys_common.h" 7990 #include "system/common/sys_module.h" 8060 #ifndef _PLIB_DMA_PROCESSOR_H 8061 #define _PLIB_DMA_PROCESSOR_H 8062 #error "Can't find header" 8106 DMA_MODULE_ID index ,
8107 DMA_CHANNEL channel ) ;
8141 DMA_MODULE_ID index ,
8142 DMA_CHANNEL channel ,
8143 DMA_CHANNEL_COLLISION collisonType ) ;
8175 DMA_MODULE_ID index ,
8176 DMA_CHANNEL channel ) ;
8208 DMA_MODULE_ID index ,
8209 DMA_CHANNEL channel ) ;
8247 DMA_MODULE_ID index ,
8248 DMA_CHANNEL channel ,
8249 DMA_CHANNEL_PRIORITY channelPriority ) ;
8278 DMA_CHANNEL_PRIORITY
8280 DMA_MODULE_ID index ,
8281 DMA_CHANNEL channel ) ;
8309 DMA_MODULE_ID index ,
8310 DMA_CHANNEL_PRIORITY channelPriority ) ;
8335 DMA_CHANNEL_PRIORITY
8337 DMA_MODULE_ID index ) ;
8367 DMA_MODULE_ID index ,
8368 DMA_CHANNEL channel ) ;
8399 DMA_MODULE_ID index ,
8400 DMA_CHANNEL channel ) ;
8429 DMA_MODULE_ID index ,
8430 DMA_CHANNEL channel ) ;
8459 DMA_MODULE_ID index ,
8460 DMA_CHANNEL channel ) ;
8491 DMA_MODULE_ID index ,
8492 DMA_CHANNEL channel ) ;
8521 DMA_MODULE_ID index ,
8522 DMA_CHANNEL channel ) ;
8553 DMA_MODULE_ID index ,
8554 DMA_CHANNEL channel ) ;
8585 DMA_MODULE_ID index ,
8586 DMA_CHANNEL channel ) ;
8615 DMA_MODULE_ID index ,
8616 DMA_CHANNEL channel ) ;
8647 DMA_MODULE_ID index ,
8648 DMA_CHANNEL channel ) ;
8677 DMA_MODULE_ID index ,
8678 DMA_CHANNEL channel ) ;
8708 DMA_MODULE_ID index ,
8709 DMA_CHANNEL channel ) ;
8739 DMA_MODULE_ID index ,
8740 DMA_CHANNEL channel ) ;
8770 DMA_MODULE_ID index ,
8771 DMA_CHANNEL channel ) ;
8801 DMA_MODULE_ID index ,
8802 DMA_CHANNEL channel ) ;
8833 DMA_MODULE_ID index ,
8834 DMA_CHANNEL channel ) ;
8865 DMA_MODULE_ID index ,
8866 DMA_CHANNEL channel ,
8867 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8896 DMA_CHANNEL_TRANSFER_DIRECTION
8898 DMA_MODULE_ID index ,
8899 DMA_CHANNEL channel ) ;
8935 DMA_MODULE_ID index ,
8936 DMA_CHANNEL channel ,
8938 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8971 DMA_MODULE_ID index ,
8972 DMA_CHANNEL channel ,
8973 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9004 DMA_MODULE_ID index ,
9005 DMA_CHANNEL channel ,
9006 uint16_t peripheraladdress ) ;
9034 DMA_MODULE_ID index ,
9035 DMA_CHANNEL channel ) ;
9066 DMA_MODULE_ID index ,
9067 DMA_CHANNEL channel ,
9068 uint16_t transferCount ) ;
9096 DMA_MODULE_ID index ,
9097 DMA_CHANNEL channel ) ;
9130 DMA_MODULE_ID index ,
9131 DMA_CHANNEL channel ,
9132 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9160 DMA_SOURCE_ADDRESSING_MODE
9162 DMA_MODULE_ID index ,
9163 DMA_CHANNEL channel ) ;
9196 DMA_MODULE_ID index ,
9197 DMA_CHANNEL channel ,
9198 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9227 DMA_DESTINATION_ADDRESSING_MODE
9229 DMA_MODULE_ID index ,
9230 DMA_CHANNEL channel ) ;
9263 DMA_MODULE_ID index ,
9264 DMA_CHANNEL channel ,
9265 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9293 DMA_CHANNEL_ADDRESSING_MODE
9295 DMA_MODULE_ID index ,
9296 DMA_CHANNEL channel ) ;
9334 DMA_MODULE_ID index ,
9335 DMA_CHANNEL channel ,
9336 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9372 DMA_MODULE_ID index ,
9373 DMA_CHANNEL channel ,
9374 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9409 DMA_MODULE_ID index ,
9410 DMA_CHANNEL channel ,
9411 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9440 DMA_CHANNEL_INT_SOURCE
9442 DMA_MODULE_ID index ,
9443 DMA_CHANNEL channel ) ;
9478 DMA_MODULE_ID index ,
9479 DMA_CHANNEL channel ,
9480 DMA_TRIGGER_SOURCE IRQnum ) ;
9515 DMA_MODULE_ID index ,
9516 DMA_CHANNEL channel ,
9517 DMA_TRIGGER_SOURCE IRQ ) ;
9548 DMA_MODULE_ID index ,
9549 DMA_CHANNEL channel ,
9550 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9577 DMA_CHANNEL_DATA_SIZE
9579 DMA_MODULE_ID index ,
9580 DMA_CHANNEL channel ) ;
9614 DMA_MODULE_ID index ,
9615 DMA_CHANNEL channel ,
9616 DMA_TRANSFER_MODE channeltransferMode ) ;
9648 DMA_MODULE_ID index ,
9649 DMA_CHANNEL channel ) ;
9678 DMA_MODULE_ID index ,
9679 DMA_CHANNEL channel ) ;
9709 DMA_MODULE_ID index ,
9710 DMA_CHANNEL channel ) ;
9739 DMA_MODULE_ID index ,
9740 DMA_CHANNEL channel ) ;
9768 DMA_MODULE_ID index ,
9769 DMA_CHANNEL channel ) ;
9799 DMA_MODULE_ID index ,
9800 DMA_CHANNEL channel ) ;
9827 DMA_MODULE_ID index ,
9828 DMA_CHANNEL channel ) ;
9864 DMA_MODULE_ID index ,
9865 DMA_CHANNEL channel ) ;
9896 DMA_MODULE_ID index ,
9897 DMA_CHANNEL channel ) ;
9930 DMA_MODULE_ID index ) ;
9959 DMA_MODULE_ID index ) ;
9989 DMA_MODULE_ID index ) ;
10018 DMA_MODULE_ID index ) ;
10047 DMA_MODULE_ID index ) ;
10077 DMA_MODULE_ID index ) ;
10105 DMA_MODULE_ID index ) ;
10133 DMA_MODULE_ID index ) ;
10161 DMA_MODULE_ID index ) ;
10190 DMA_MODULE_ID index ) ;
10218 DMA_MODULE_ID index ) ;
10252 DMA_MODULE_ID index ) ;
10282 DMA_MODULE_ID index ) ;
10312 DMA_MODULE_ID index ) ;
10341 DMA_MODULE_ID index ) ;
10376 DMA_MODULE_ID index ,
10377 DMA_CHANNEL channel ) ;
10406 DMA_MODULE_ID index ) ;
10438 DMA_MODULE_ID index ,
10439 DMA_CRC_TYPE CRCType ) ;
10470 DMA_MODULE_ID index ) ;
10500 DMA_MODULE_ID index ) ;
10530 DMA_MODULE_ID index ) ;
10560 DMA_MODULE_ID index ) ;
10589 DMA_MODULE_ID index ) ;
10619 DMA_MODULE_ID index ) ;
10648 DMA_MODULE_ID index ) ;
10678 DMA_MODULE_ID index ,
10679 uint8_t polyLength ) ;
10708 DMA_MODULE_ID index ) ;
10737 DMA_MODULE_ID index ,
10738 DMA_CRC_BIT_ORDER bitOrder ) ;
10769 DMA_MODULE_ID index ) ;
10798 DMA_MODULE_ID index ) ;
10828 DMA_MODULE_ID index ,
10829 DMA_CRC_BYTE_ORDER byteOrder ) ;
10858 DMA_MODULE_ID index ) ;
10889 DMA_MODULE_ID index ) ;
10921 DMA_MODULE_ID index ,
10922 uint32_t DMACRCdata ) ;
10953 DMA_MODULE_ID index ) ;
10986 DMA_MODULE_ID index ,
10987 uint32_t DMACRCXOREnableMask ) ;
11025 DMA_MODULE_ID index ,
11026 DMA_CHANNEL dmaChannel ) ;
11063 DMA_MODULE_ID index ,
11064 DMA_CHANNEL dmaChannel ,
11065 uint32_t sourceStartAddress ) ;
11099 DMA_MODULE_ID index ,
11100 DMA_CHANNEL dmaChannel ) ;
11138 DMA_MODULE_ID index ,
11139 DMA_CHANNEL dmaChannel ,
11140 uint32_t destinationStartAddress ) ;
11180 DMA_MODULE_ID index ,
11181 DMA_CHANNEL dmaChannel ) ;
11220 DMA_MODULE_ID index ,
11221 DMA_CHANNEL dmaChannel ,
11222 uint16_t sourceSize ) ;
11257 DMA_MODULE_ID index ,
11258 DMA_CHANNEL dmaChannel ) ;
11295 DMA_MODULE_ID index ,
11296 DMA_CHANNEL dmaChannel ,
11297 uint16_t destinationSize ) ;
11331 DMA_MODULE_ID index ,
11332 DMA_CHANNEL dmaChannel ) ;
11367 DMA_MODULE_ID index ,
11368 DMA_CHANNEL dmaChannel ) ;
11403 DMA_MODULE_ID index ,
11404 DMA_CHANNEL dmaChannel ) ;
11441 DMA_MODULE_ID index ,
11442 DMA_CHANNEL dmaChannel ,
11443 uint16_t CellSize ) ;
11477 DMA_MODULE_ID index ,
11478 DMA_CHANNEL dmaChannel ) ;
11515 DMA_MODULE_ID index ,
11516 DMA_CHANNEL dmaChannel ) ;
11555 DMA_MODULE_ID index ,
11556 DMA_CHANNEL dmaChannel ,
11557 uint16_t patternData ) ;
11601 DMA_MODULE_ID index ,
11602 DMA_CHANNEL dmaChannel ,
11603 DMA_INT_TYPE dmaINTSource ) ;
11638 DMA_MODULE_ID index ,
11639 DMA_CHANNEL dmaChannel ,
11640 DMA_INT_TYPE dmaINTSource ) ;
11676 DMA_MODULE_ID index ,
11677 DMA_CHANNEL dmaChannel ,
11678 DMA_INT_TYPE dmaINTSource ) ;
11712 DMA_MODULE_ID index ,
11713 DMA_CHANNEL dmaChannel ,
11714 DMA_INT_TYPE dmaINTSource ) ;
11748 DMA_MODULE_ID index ,
11749 DMA_CHANNEL dmaChannel ,
11750 DMA_INT_TYPE dmaINTSource ) ;
11788 DMA_MODULE_ID index ,
11789 DMA_CHANNEL dmaChannel ,
11790 DMA_INT_TYPE dmaINTSource ) ;
11823 DMA_MODULE_ID index ,
11824 DMA_CHANNEL dmaChannel ,
11825 DMA_PATTERN_LENGTH patternLen ) ;
11858 DMA_MODULE_ID index ,
11859 DMA_CHANNEL dmaChannel ) ;
11889 DMA_MODULE_ID index ,
11890 DMA_CHANNEL channel ) ;
11923 DMA_MODULE_ID index ,
11924 DMA_CHANNEL channel ) ;
11954 DMA_MODULE_ID index ,
11955 DMA_CHANNEL channel ) ;
11987 DMA_MODULE_ID index ,
11988 DMA_CHANNEL channel ,
11989 uint8_t pattern ) ;
12020 DMA_MODULE_ID index ,
12021 DMA_CHANNEL channel ) ;
12053 DMA_MODULE_ID index ) ;
12078 DMA_MODULE_ID index ) ;
12102 DMA_MODULE_ID index ) ;
12127 DMA_MODULE_ID index ) ;
12150 DMA_MODULE_ID index ) ;
12174 DMA_MODULE_ID index ) ;
12197 DMA_MODULE_ID index ) ;
12221 DMA_MODULE_ID index ) ;
12245 DMA_MODULE_ID index ) ;
12270 DMA_MODULE_ID index ) ;
12294 DMA_MODULE_ID index ) ;
12318 DMA_MODULE_ID index ) ;
12341 DMA_MODULE_ID index ) ;
12365 DMA_MODULE_ID index ) ;
12389 DMA_MODULE_ID index ) ;
12413 DMA_MODULE_ID index ) ;
12437 DMA_MODULE_ID index ) ;
12461 DMA_MODULE_ID index ) ;
12484 DMA_MODULE_ID index ) ;
12509 DMA_MODULE_ID index ) ;
12534 DMA_MODULE_ID index ) ;
12558 DMA_MODULE_ID index ) ;
12583 DMA_MODULE_ID index ) ;
12607 DMA_MODULE_ID index ) ;
12631 DMA_MODULE_ID index ) ;
12657 DMA_MODULE_ID index ) ;
12682 DMA_MODULE_ID index ) ;
12706 DMA_MODULE_ID index ) ;
12731 DMA_MODULE_ID index ) ;
12754 DMA_MODULE_ID index ) ;
12777 DMA_MODULE_ID index ) ;
12800 DMA_MODULE_ID index ) ;
12823 DMA_MODULE_ID index ) ;
12848 DMA_MODULE_ID index ) ;
12873 DMA_MODULE_ID index ) ;
12897 DMA_MODULE_ID index ) ;
12922 DMA_MODULE_ID index ) ;
12946 DMA_MODULE_ID index ) ;
12970 DMA_MODULE_ID index ) ;
12993 DMA_MODULE_ID index ) ;
13016 DMA_MODULE_ID index ) ;
13040 DMA_MODULE_ID index ) ;
13064 DMA_MODULE_ID index ) ;
13088 DMA_MODULE_ID index ) ;
13115 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13128 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13141 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13171 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13345 DMA_CRC_TYPE type ;
13351 uint8_t polyLength ;
13354 DMA_CRC_BIT_ORDER bitOrder ;
13357 DMA_CRC_BYTE_ORDER byteOrder ;
13367 uint32_t xorBitMask ;
13492 SYS_MODULE_OBJ
object ,
13493 DMA_CHANNEL activeChannel ) ;
13496 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13541 uintptr_t contextHandle ) ;
13587 const SYS_MODULE_INIT *
const init ) ;
13638 DMA_CHANNEL channel ) ;
13724 DMA_TRIGGER_SOURCE eventSrc ) ;
13802 DMA_PATTERN_LENGTH length ,
13804 uint8_t ignorePattern ) ;
14057 const void * srcAddr ,
14059 const void * destAddr ,
14061 size_t cellSize ) ;
14158 const void * srcAddr ,
14160 const void * destAddr ,
14162 size_t cellSize ) ;
14358 const uintptr_t contextHandle ) ;
14654 DMA_TRIGGER_SOURCE eventSrc ) ;
14833 SYS_MODULE_OBJ
object ,
14834 DMA_CHANNEL activeChannel ) ;
14844 SYS_MODULE_OBJ
object ) ;
14854 SYS_MODULE_OBJ
object ,
14855 DMA_CHANNEL activeChannel ) ;
14882 #define DRV_USART_INDEX_0 0 14883 #define DRV_USART_INDEX_1 1 14884 #define DRV_USART_INDEX_2 2 14885 #define DRV_USART_INDEX_3 3 14886 #define DRV_USART_INDEX_4 4 14887 #define DRV_USART_INDEX_5 5 14901 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14912 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14923 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14957 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15108 uintptr_t context ) ;
15156 USART_HANDSHAKE_MODE_FLOW_CONTROL
15160 USART_HANDSHAKE_MODE_SIMPLEX
15322 } AddressedModeInit ;
15347 = USART_ERROR_PARITY
15352 = USART_ERROR_FRAMING
15357 = USART_ERROR_RECEIVER_OVERRUN
15439 SYS_MODULE_INIT moduleInit ;
15443 USART_MODULE_ID usartID ;
15461 uint32_t brgClock ;
15477 USART_OPERATION_MODE linesEnable ;
15481 INT_SOURCE interruptTransmit ;
15485 INT_SOURCE interruptReceive ;
15489 INT_SOURCE interruptError ;
15494 unsigned int queueSizeReceive ;
15499 unsigned int queueSizeTransmit ;
15503 DMA_CHANNEL dmaChannelTransmit ;
15507 DMA_CHANNEL dmaChannelReceive ;
15511 INT_SOURCE dmaInterruptTransmit ;
15515 INT_SOURCE dmaInterruptReceive ;
15599 const SYS_MODULE_INDEX index ,
15600 const SYS_MODULE_INIT *
const init ) ;
15638 SYS_MODULE_OBJ
object ) ;
15676 SYS_MODULE_OBJ
object ) ;
15717 SYS_MODULE_OBJ
object ) ;
15758 SYS_MODULE_OBJ
object ) ;
15799 SYS_MODULE_OBJ
object ) ;
15878 const SYS_MODULE_INDEX index ,
16062 const size_t size ) ;
16255 const size_t size ) ;
16343 const uintptr_t context ) ;
16610 const size_t numbytes ) ;
16678 const size_t numbytes ) ;
16815 const uint8_t byte ) ;
17033 const SYS_MODULE_INDEX index ,
17086 const SYS_MODULE_INDEX index ,
17135 const SYS_MODULE_INDEX index ,
17350 #ifndef _DRV_USART_FEATURE_MAPPING_H 17351 #define _DRV_USART_FEATURE_MAPPING_H 17360 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17361 #define _DRV_USART_InterruptSourceEnable( source ) 17362 #define _DRV_USART_InterruptSourceDisable( source ) false 17363 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17364 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17365 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17366 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17367 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17370 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17379 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17380 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17381 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17382 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17383 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17396 #include "system/clk/sys_clk.h" 17397 #include "system/int/sys_int.h" 17435 #ifndef _SYS_DEBUG_H 17436 #define _SYS_DEBUG_H 17437 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17440 #define SYS_DEBUG_BUFFER_DMA_READY 17490 #define SYS_DEBUG_INDEX_0 0 17506 SYS_MODULE_INIT moduleInit ;
17510 SYS_MODULE_INDEX consoleIndex ;
17558 const SYS_MODULE_INDEX index ,
17559 const SYS_MODULE_INIT *
const init ) ;
17599 SYS_MODULE_OBJ
object ,
17600 const SYS_MODULE_INIT *
const init ) ;
17630 SYS_MODULE_OBJ
object ) ;
17663 SYS_MODULE_OBJ
object ) ;
17707 SYS_MODULE_OBJ
object ) ;
17750 const char * message ) ;
17800 const char * format ,
17890 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17934 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17977 #define SYS_MESSAGE( message ) 18010 #define SYS_DEBUG_MESSAGE( level , message ) 18057 #define SYS_PRINT( fmt ,... ) 18105 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18130 #define SYS_DEBUG_BreakPoint( ) 18139 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18140 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18141 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18158 #define _DRV_USART_RX_DEPTH 9 18224 const SYS_MODULE_INDEX index ,
18249 const uint8_t byte ) ;
18320 #ifndef _SYS_PORTS_H 18321 #define _SYS_PORTS_H 18360 #ifndef _SYS_PORTS_DEFINITIONS_H 18361 #define _SYS_PORTS_DEFINITIONS_H 18367 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18368 #include "system/common/sys_common.h" 18369 #include "system/common/sys_module.h" 18406 #ifndef _PLIB_PORTS_H 18407 #define _PLIB_PORTS_H 18408 #include <stdint.h> 18409 #include <stddef.h> 18474 #ifndef _PLIB_PORTS_PROCESSOR_H 18475 #define _PLIB_PORTS_PROCESSOR_H 18476 #error "Can't find header" 18526 PORTS_MODULE_ID index ,
18527 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18528 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18571 PORTS_MODULE_ID index ,
18572 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18573 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18608 PORTS_MODULE_ID index ,
18609 PORTS_ANALOG_PIN pin ,
18610 PORTS_PIN_MODE mode ) ;
18650 PORTS_MODULE_ID index ,
18651 PORTS_CHANNEL channel ,
18652 PORTS_BIT_POS bitPos ,
18653 PORTS_PIN_MODE mode ) ;
18688 PORTS_MODULE_ID index ,
18689 PORTS_CHANNEL channel ,
18690 PORTS_BIT_POS bitPos ) ;
18724 PORTS_MODULE_ID index ,
18725 PORTS_CHANNEL channel ,
18726 PORTS_BIT_POS bitPos ) ;
18763 PORTS_MODULE_ID index ,
18764 PORTS_CHANNEL channel ,
18765 PORTS_BIT_POS bitPos ) ;
18806 PORTS_MODULE_ID index ,
18807 PORTS_CHANNEL channel ,
18808 PORTS_BIT_POS bitPos ) ;
18847 PORTS_MODULE_ID index ,
18848 PORTS_CHANNEL channel ,
18849 PORTS_BIT_POS bitPos ) ;
18887 PORTS_MODULE_ID index ,
18888 PORTS_CHANNEL channel ,
18889 PORTS_BIT_POS bitPos ) ;
18924 PORTS_MODULE_ID index ,
18925 PORTS_CHANNEL channel ) ;
18960 PORTS_MODULE_ID index ,
18961 PORTS_CHANNEL channel ) ;
18998 PORTS_MODULE_ID index ,
18999 PORTS_CHANNEL channel ) ;
19036 PORTS_MODULE_ID index ,
19037 PORTS_CHANNEL channel ) ;
19074 PORTS_MODULE_ID index ,
19075 PORTS_CHANNEL channel ,
19076 PORTS_BIT_POS bitPos ) ;
19113 PORTS_MODULE_ID index ,
19114 PORTS_CHANNEL channel ,
19115 PORTS_BIT_POS bitPos ) ;
19153 PORTS_MODULE_ID index ,
19154 PORTS_CHANNEL channel ,
19155 PORTS_BIT_POS bitPos ) ;
19192 PORTS_MODULE_ID index ,
19193 PORTS_CHANNEL channel ,
19194 PORTS_BIT_POS bitPos ,
19229 PORTS_MODULE_ID index ,
19230 PORTS_CHANNEL channel ,
19231 PORTS_BIT_POS bitPos ) ;
19265 PORTS_MODULE_ID index ,
19266 PORTS_CHANNEL channel ,
19267 PORTS_BIT_POS bitPos ) ;
19301 PORTS_MODULE_ID index ,
19302 PORTS_CHANNEL channel ,
19303 PORTS_BIT_POS bitPos ) ;
19338 PORTS_MODULE_ID index ,
19339 PORTS_CHANNEL channel ,
19340 PORTS_BIT_POS bitPos ) ;
19375 PORTS_MODULE_ID index ,
19376 PORTS_CHANNEL channel ,
19377 PORTS_BIT_POS bitPos ) ;
19411 PORTS_MODULE_ID index ,
19412 PORTS_CHANNEL channel ,
19413 PORTS_BIT_POS bitPos ) ;
19447 PORTS_MODULE_ID index ,
19448 PORTS_CHANNEL channel ,
19449 PORTS_BIT_POS bitPos ) ;
19487 PORTS_MODULE_ID index ,
19488 PORTS_CHANNEL channel ) ;
19522 PORTS_MODULE_ID index ,
19523 PORTS_CHANNEL channel ) ;
19557 PORTS_MODULE_ID index ,
19558 PORTS_CHANNEL channel ,
19601 PORTS_MODULE_ID index ,
19602 PORTS_CHANNEL channel ,
19638 PORTS_MODULE_ID index ,
19639 PORTS_CHANNEL channel ,
19674 PORTS_MODULE_ID index ,
19675 PORTS_CHANNEL channel ,
19711 PORTS_MODULE_ID index ,
19712 PORTS_CHANNEL channel ,
19747 PORTS_MODULE_ID index ,
19748 PORTS_CHANNEL channel ,
19781 PORTS_MODULE_ID index ,
19782 PORTS_CHANNEL channel ) ;
19816 PORTS_MODULE_ID index ,
19817 PORTS_CHANNEL channel ,
19853 PORTS_MODULE_ID index ,
19854 PORTS_CHANNEL channel ,
19900 PORTS_MODULE_ID index ,
19901 PORTS_CHANNEL channel ,
19903 PORTS_PIN_MODE mode ) ;
19945 PORTS_MODULE_ID index ,
19946 PORTS_CHANNEL channel ,
19989 PORTS_MODULE_ID index ,
19990 PORTS_CHANNEL channel ,
20030 PORTS_MODULE_ID index ,
20031 PORTS_CHANNEL channel ,
20071 PORTS_MODULE_ID index ,
20072 PORTS_CHANNEL channel ,
20116 PORTS_MODULE_ID index ,
20117 PORTS_CHANNEL channel ,
20161 PORTS_MODULE_ID index ,
20162 PORTS_CHANNEL channel ,
20208 PORTS_MODULE_ID index ,
20209 PORTS_AN_PIN anPins ,
20210 PORTS_PIN_MODE mode ) ;
20253 PORTS_MODULE_ID index ,
20254 PORTS_CN_PIN cnPins ) ;
20298 PORTS_MODULE_ID index ,
20299 PORTS_CN_PIN cnPins ) ;
20342 PORTS_MODULE_ID index ,
20343 PORTS_CN_PIN cnPins ) ;
20386 PORTS_MODULE_ID index ,
20387 PORTS_CN_PIN cnPins ) ;
20421 PORTS_MODULE_ID index ) ;
20454 PORTS_MODULE_ID index ) ;
20490 PORTS_MODULE_ID index ,
20491 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20527 PORTS_MODULE_ID index ,
20528 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20565 PORTS_MODULE_ID index ) ;
20599 PORTS_MODULE_ID index ) ;
20635 PORTS_MODULE_ID index ,
20636 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20672 PORTS_MODULE_ID index ,
20673 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20718 PORTS_MODULE_ID index ,
20719 PORTS_CHANNEL channel ,
20721 PORTS_PIN_SLEW_RATE slewRate ) ;
20758 PORTS_PIN_SLEW_RATE
20760 PORTS_MODULE_ID index ,
20761 PORTS_CHANNEL channel ,
20762 PORTS_BIT_POS bitPos ) ;
20801 PORTS_MODULE_ID index ,
20802 PORTS_CHANNEL channel ,
20803 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20836 PORTS_CHANGE_NOTICE_METHOD
20838 PORTS_MODULE_ID index ,
20839 PORTS_CHANNEL channel ) ;
20887 PORTS_MODULE_ID index ,
20888 PORTS_CHANNEL channel ,
20938 PORTS_MODULE_ID index ,
20939 PORTS_CHANNEL channel ,
20987 PORTS_MODULE_ID index ,
20988 PORTS_CHANNEL channel ,
20989 PORTS_BIT_POS bitPos ,
20990 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21033 PORTS_MODULE_ID index ,
21034 PORTS_CHANNEL channel ,
21035 PORTS_BIT_POS bitPos ) ;
21066 PORTS_MODULE_ID index ) ;
21090 PORTS_MODULE_ID index ) ;
21114 PORTS_MODULE_ID index ) ;
21138 PORTS_MODULE_ID index ) ;
21163 PORTS_MODULE_ID index ) ;
21188 PORTS_MODULE_ID index ) ;
21219 PORTS_MODULE_ID index ) ;
21247 PORTS_MODULE_ID index ) ;
21274 PORTS_MODULE_ID index ) ;
21299 PORTS_MODULE_ID index ) ;
21326 PORTS_MODULE_ID index ) ;
21351 PORTS_MODULE_ID index ) ;
21378 PORTS_MODULE_ID index ) ;
21403 PORTS_MODULE_ID index ) ;
21431 PORTS_MODULE_ID index ) ;
21459 PORTS_MODULE_ID index ) ;
21487 PORTS_MODULE_ID index ) ;
21513 PORTS_MODULE_ID index ) ;
21539 PORTS_MODULE_ID index ) ;
21565 PORTS_MODULE_ID index ) ;
21590 PORTS_MODULE_ID index ) ;
21616 PORTS_MODULE_ID index ) ;
21643 PORTS_MODULE_ID index ) ;
21668 PORTS_MODULE_ID index ) ;
21703 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21704 #define _PLIB_PORTS_COMPATIBILITY_H 21705 #include <stdint.h> 21706 #include <stddef.h> 21741 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21758 #include "system/int/sys_int.h" 21892 PORTS_MODULE_ID index ,
21893 PORTS_CHANNEL channel ) ;
21925 PORTS_MODULE_ID index ,
21926 PORTS_CHANNEL channel ,
21956 PORTS_MODULE_ID index ,
21957 PORTS_CHANNEL channel ) ;
21995 PORTS_MODULE_ID index ,
21996 PORTS_CHANNEL channel ,
22030 PORTS_MODULE_ID index ,
22031 PORTS_CHANNEL channel ,
22068 PORTS_MODULE_ID index ,
22070 PORTS_CHANNEL channel ,
22100 PORTS_MODULE_ID index ,
22101 PORTS_CHANNEL channel ) ;
22132 PORTS_MODULE_ID index ,
22133 PORTS_CHANNEL channel ,
22165 PORTS_MODULE_ID index ,
22166 PORTS_CHANNEL channel ,
22198 PORTS_MODULE_ID index ,
22199 PORTS_CHANNEL channel ,
22233 PORTS_MODULE_ID index ,
22234 PORTS_CHANNEL channel ) ;
22274 PORTS_MODULE_ID index ,
22275 PORTS_REMAP_INPUT_FUNCTION
function ,
22276 PORTS_REMAP_INPUT_PIN remapPin ) ;
22311 PORTS_MODULE_ID index ,
22312 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22313 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22346 PORTS_MODULE_ID index ) ;
22374 PORTS_MODULE_ID index ) ;
22408 PORTS_MODULE_ID index ,
22409 PORTS_CHANGE_NOTICE_PIN pinNum ,
22441 PORTS_MODULE_ID index ,
22442 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22471 PORTS_MODULE_ID index ) ;
22500 PORTS_MODULE_ID index ) ;
22531 PORTS_MODULE_ID index ,
22532 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22563 PORTS_MODULE_ID index ,
22564 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22603 PORTS_MODULE_ID index ,
22604 PORTS_ANALOG_PIN pin ,
22605 PORTS_PIN_MODE mode ) ;
22642 PORTS_MODULE_ID index ,
22643 PORTS_CHANNEL channel ,
22644 PORTS_BIT_POS bitPos ,
22679 PORTS_MODULE_ID index ,
22680 PORTS_CHANNEL channel ,
22681 PORTS_BIT_POS bitPos ) ;
22714 PORTS_MODULE_ID index ,
22715 PORTS_CHANNEL channel ,
22716 PORTS_BIT_POS bitPos ) ;
22749 PORTS_MODULE_ID index ,
22750 PORTS_CHANNEL channel ,
22751 PORTS_BIT_POS bitPos ) ;
22784 PORTS_MODULE_ID index ,
22785 PORTS_CHANNEL channel ,
22786 PORTS_BIT_POS bitPos ) ;
22819 PORTS_MODULE_ID index ,
22820 PORTS_CHANNEL channel ,
22821 PORTS_BIT_POS bitPos ) ;
22858 PORTS_MODULE_ID index ,
22860 PORTS_CHANNEL channel ,
22861 PORTS_BIT_POS bitPos ) ;
22894 PORTS_MODULE_ID index ,
22895 PORTS_CHANNEL channel ,
22896 PORTS_BIT_POS bitPos ) ;
22929 PORTS_MODULE_ID index ,
22930 PORTS_CHANNEL channel ,
22931 PORTS_BIT_POS bitPos ) ;
22964 PORTS_MODULE_ID index ,
22965 PORTS_CHANNEL channel ,
22966 PORTS_BIT_POS bitPos ) ;
22999 PORTS_MODULE_ID index ,
23000 PORTS_CHANNEL channel ,
23001 PORTS_BIT_POS bitPos ) ;
23034 PORTS_MODULE_ID index ,
23035 PORTS_CHANNEL channel ,
23036 PORTS_BIT_POS bitPos ) ;
23069 PORTS_MODULE_ID index ,
23070 PORTS_CHANNEL channel ,
23071 PORTS_BIT_POS bitPos ) ;
23104 PORTS_MODULE_ID index ,
23105 PORTS_CHANNEL channel ,
23106 PORTS_BIT_POS bitPos ,
23189 #ifndef _DRV_SPI_DEFINITIONS_H 23190 #define _DRV_SPI_DEFINITIONS_H 23196 #include <stdint.h> 23197 #include <stdbool.h> 23198 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23199 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23235 #ifndef _PLIB_SPI_H 23236 #define _PLIB_SPI_H 23270 #ifndef _PLIB_SPI_PROCESSOR_H 23271 #define _PLIB_SPI_PROCESSOR_H 23272 #error "Can't find header" 23317 SPI_MODULE_ID index ) ;
23347 SPI_MODULE_ID index ) ;
23379 SPI_MODULE_ID index ) ;
23411 SPI_MODULE_ID index ) ;
23445 SPI_MODULE_ID index ) ;
23475 SPI_MODULE_ID index ) ;
23512 SPI_MODULE_ID index ) ;
23551 SPI_MODULE_ID index ) ;
23581 SPI_MODULE_ID index ,
23612 SPI_MODULE_ID index ,
23646 SPI_MODULE_ID index ,
23647 SPI_COMMUNICATION_WIDTH width ) ;
23682 SPI_MODULE_ID index ,
23683 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23715 SPI_MODULE_ID index ,
23716 SPI_INPUT_SAMPLING_PHASE phase ) ;
23748 SPI_MODULE_ID index ,
23749 SPI_OUTPUT_DATA_PHASE phase ) ;
23780 SPI_MODULE_ID index ,
23781 SPI_CLOCK_POLARITY polarity ) ;
23811 SPI_MODULE_ID index ) ;
23841 SPI_MODULE_ID index ) ;
23879 SPI_MODULE_ID index ,
23880 uint32_t clockFrequency ,
23881 uint32_t baudRate ) ;
23912 SPI_MODULE_ID index ) ;
23944 SPI_MODULE_ID index ) ;
23977 SPI_MODULE_ID index ) ;
24010 SPI_MODULE_ID index ) ;
24042 SPI_MODULE_ID index ) ;
24072 SPI_MODULE_ID index ) ;
24103 SPI_MODULE_ID index ) ;
24134 SPI_MODULE_ID index ) ;
24165 SPI_MODULE_ID index ) ;
24197 SPI_MODULE_ID index ,
24198 SPI_FIFO_TYPE type ) ;
24230 SPI_MODULE_ID index ) ;
24262 SPI_MODULE_ID index ) ;
24296 SPI_MODULE_ID index ,
24297 SPI_FIFO_INTERRUPT mode ) ;
24327 SPI_MODULE_ID index ) ;
24357 SPI_MODULE_ID index ) ;
24389 SPI_MODULE_ID index ,
24390 SPI_FRAME_PULSE_DIRECTION direction ) ;
24423 SPI_MODULE_ID index ,
24424 SPI_FRAME_PULSE_POLARITY polarity ) ;
24457 SPI_MODULE_ID index ,
24458 SPI_FRAME_PULSE_EDGE edge ) ;
24491 SPI_MODULE_ID index ,
24492 SPI_FRAME_PULSE_WIDTH width ) ;
24526 SPI_MODULE_ID index ,
24527 SPI_FRAME_SYNC_PULSE pulse ) ;
24559 SPI_MODULE_ID index ) ;
24589 SPI_MODULE_ID index ) ;
24621 SPI_MODULE_ID index ) ;
24651 SPI_MODULE_ID index ) ;
24681 SPI_MODULE_ID index ) ;
24711 SPI_MODULE_ID index ) ;
24742 SPI_MODULE_ID index ,
24774 SPI_MODULE_ID index ,
24806 SPI_MODULE_ID index ,
24829 SPI_MODULE_ID index ) ;
24860 SPI_MODULE_ID index ,
24861 SPI_BAUD_RATE_CLOCK type ) ;
24893 SPI_MODULE_ID index ,
24894 SPI_ERROR_INTERRUPT error ) ;
24926 SPI_MODULE_ID index ,
24927 SPI_ERROR_INTERRUPT error ) ;
24958 SPI_MODULE_ID index ,
24959 SPI_AUDIO_ERROR error ) ;
24990 SPI_MODULE_ID index ,
24991 SPI_AUDIO_ERROR error ) ;
25021 SPI_MODULE_ID index ) ;
25051 SPI_MODULE_ID index ) ;
25083 SPI_MODULE_ID index ,
25084 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25116 SPI_MODULE_ID index ,
25117 SPI_AUDIO_PROTOCOL mode ) ;
25150 SPI_MODULE_ID index ) ;
25176 SPI_MODULE_ID index ) ;
25202 SPI_MODULE_ID index ) ;
25227 SPI_MODULE_ID index ) ;
25252 SPI_MODULE_ID index ) ;
25277 SPI_MODULE_ID index ) ;
25303 SPI_MODULE_ID index ) ;
25328 SPI_MODULE_ID index ) ;
25353 SPI_MODULE_ID index ) ;
25378 SPI_MODULE_ID index ) ;
25403 SPI_MODULE_ID index ) ;
25428 SPI_MODULE_ID index ) ;
25454 SPI_MODULE_ID index ) ;
25479 SPI_MODULE_ID index ) ;
25504 SPI_MODULE_ID index ) ;
25529 SPI_MODULE_ID index ) ;
25555 SPI_MODULE_ID index ) ;
25581 SPI_MODULE_ID index ) ;
25607 SPI_MODULE_ID index ) ;
25631 SPI_MODULE_ID index ) ;
25656 SPI_MODULE_ID index ) ;
25681 SPI_MODULE_ID index ) ;
25706 SPI_MODULE_ID index ) ;
25732 SPI_MODULE_ID index ) ;
25757 SPI_MODULE_ID index ) ;
25782 SPI_MODULE_ID index ) ;
25807 SPI_MODULE_ID index ) ;
25832 SPI_MODULE_ID index ) ;
25857 SPI_MODULE_ID index ) ;
25883 SPI_MODULE_ID index ) ;
25910 SPI_MODULE_ID index ) ;
25935 SPI_MODULE_ID index ) ;
25961 SPI_MODULE_ID index ) ;
25987 SPI_MODULE_ID index ) ;
26013 SPI_MODULE_ID index ) ;
26038 SPI_MODULE_ID index ) ;
26063 SPI_MODULE_ID index ) ;
26089 SPI_MODULE_ID index ) ;
26115 SPI_MODULE_ID index ) ;
26127 #include "system/common/sys_common.h" 26128 #include "system/common/sys_module.h" 26129 #include "system/int/sys_int.h" 26130 #include "system/clk/sys_clk.h" 26131 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26169 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26181 #define DRV_SPI_INDEX_0 0 26182 #define DRV_SPI_INDEX_1 1 26183 #define DRV_SPI_INDEX_2 2 26184 #define DRV_SPI_INDEX_3 3 26185 #define DRV_SPI_INDEX_4 4 26186 #define DRV_SPI_INDEX_5 5 26198 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26447 SPI_MODULE_ID
spiId ;
26480 CLK_BUSES_PERIPHERAL
spiClk ;
26640 const SYS_MODULE_INDEX index ,
26641 const SYS_MODULE_INIT *
const init ) ;
26683 SYS_MODULE_OBJ
object ) ;
26732 SYS_MODULE_OBJ
object ) ;
26773 SYS_MODULE_OBJ
object ) ;
26838 const SYS_MODULE_INDEX drvIndex ,
27433 #include "driver/usb/usbhs/drv_usbhs.h" 27434 #include "usb/usb_device.h" 27462 #include <stdint.h> 27482 uint8_t RevNumber ;
27569 SYS_MODULE_OBJ sysTmr ;
27570 SYS_MODULE_OBJ drvTmr0 ;
27571 SYS_MODULE_OBJ drvTmr1 ;
27572 SYS_MODULE_OBJ drvTmr2 ;
27573 SYS_MODULE_OBJ drvTmr3 ;
27574 SYS_MODULE_OBJ drvTmr4 ;
27575 SYS_MODULE_OBJ drvUsart0 ;
27576 SYS_MODULE_OBJ drvPMP0 ;
27578 SYS_MODULE_OBJ spiObjectIdx0 ;
27580 SYS_MODULE_OBJ spiObjectIdx1 ;
27582 SYS_MODULE_OBJ spiObjectIdx2 ;
27583 SYS_MODULE_OBJ drvUSBObject ;
27584 SYS_MODULE_OBJ usbDevObject0 ;
27648 uint8_t null_count ;
27649 bool send_message_complete_flag ;
27656 uint8_t table_count ;
27668 uint8_t byte [ 4 ] ;
27688 uint8_t identifier ;
27690 uint8_t msg_length ;
27691 uint8_t xmit_ready_flag ;
27776 static const uint8_t
27778 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
27779 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
27780 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
27781 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
27782 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
27783 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U
27784 , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U ,
27785 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU
27786 , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU ,
27787 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U
27788 , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
27790 static const uint8_t
27792 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
27793 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
27794 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
27795 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
27796 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
27797 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
27833 uint8_t Identifier ,
27835 uint8_t Msg_Length ) ;
28048 #include <stdint.h> 28087 uint8_t thebits ) ;
28116 const uint8_t Bytes [] ) ;
28147 const uint8_t Bytes [] ) ;
28230 #include <stdbool.h> 28231 #include "../system_config.h" 28232 #include "../system_definitions.h" 28248 #define ManHalfUpper 11800U 28249 #define ManHalfLower 2000U 28250 #define ManFullUpper 20000U 28251 #define ManFullLower 11801U 28252 #define NoManBits 32U 28253 #define HalfBit 0x12U 28254 #define FullBit 0x10U 28255 #define SizeOfBiasLUT 48U 28335 uint16_t preamble [ 5 ] ;
28336 uint16_t time [ 96 ] ;
28337 uint8_t level [ 96 ] ;
28338 uint8_t ans [ 32U + 2 ] ;
28339 uint8_t msg [ 4 ] ;
28340 uint8_t cnt_preamble ;
28341 uint8_t trynumber ;
28342 bool process_complete_flag ;
28343 bool spi_write_complete_flag ;
28344 bool spi_sent_flag ;
28345 uint8_t timer_count ;
28346 uint8_t timer_complete ;
28350 bool manual_bias_flag ;
28373 uint16_t adj [ 1 ] ;
28374 uint16_t dac_a_setting ;
28375 uint16_t dac_b_setting ;
28766 #include "../system_definitions.h" 28795 int8_t v_adj [ 1 ] ;
28797 uint16_t voltage_limit ;
28799 uint16_t max_current ;
28800 uint8_t current_limit ;
28801 uint8_t upper_current_limit ;
28802 uint8_t over_current_count ;
28805 bool new_voltage_flag ;
28806 bool new_current_flag ;
28807 bool spi_write_complete_flag ;
28808 bool spi_sent_flag ;
28809 uint8_t avg_count ;
28810 uint8_t avg_count_max ;
28811 uint16_t current_array [ 5 ] ;
28812 uint16_t avg_current ;
28813 uint8_t overvoltage_count ;
28993 #include "../system_config.h" 28994 #include "../system_definitions.h" 28995 #include <stdint.h> 28996 #include <stddef.h> 29004 #define testbit( var , bit ) ( ( ( var ) & ( 1U << ( bit ) ) ) != 0U ) 29069 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
29241 uint8_t Identifier ,
29243 uint8_t Msg_Length )
29245 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 29)));
29269 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 31)));
29301 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 2)));
29502 int QZZZ = ((int)(
bitmapstruct.element4 |= (1 << 13)));
29510 (
MSG.
command ) & ( 1U << ( bit_position ) ) ) != 0U ) == 0x01U
29604 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 1)));
29622 int QZZZ = ((int)(
bitmapstruct.element5 |= (1 << 4)));
29639 int zzqqzs = ((int)(
bitmapstruct.element5 |= (1 << 5)));
29665 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 11)));
29683 int QZZZ = ((int)(
bitmapstruct.element5 |= (1 << 14)));
29700 int zzqqzs = ((int)(
bitmapstruct.element5 |= (1 << 15)));
29727 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 21)));
29737 mark = ( uint8_t ) rint (
errorMark ) ;
29753 #define qqqbranches 183 29754 #define QQQMAXMCDCSIZE 2 29758 #define ldra_sscanf 29774 #undef qqnull_params 29775 #define qqnull_params void 29777 #define qqzzidfield 1 29783 #define QQQFIXEDSIZE 29803 qqcptr = qqscan_str;
29805 while (qqcptr[0] ==
' ')
29811 if (qqcptr[0] ==
'-')
29817 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
29819 qqvalue = 10 * qqvalue;
29820 qqvalue = qqvalue + (qqcptr[0] -
'0');
29823 qqvalue = qqisign * qqvalue;
29849 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29850 ldra_port_write (&ldra_buffer[0]);
29858 ldra_port_write(s);
29866 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29867 ldra_port_write (&ldra_buffer[0]);
29875 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29876 ldra_port_write (&ldra_buffer[0]);
29884 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29885 ldra_port_write (&ldra_buffer[0]);
30004 static int branches_printed = 0;
30008 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
30009 ldra_port_write (&ldra_buffer[0]);
30010 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
30011 ldra_port_write (&ldra_buffer[0]);
30013 branches_printed += 8;
30033 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 30034 #define LASTELEMENT 30035 #include "fsk_60zbelem.def"
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
static void DRV_TMR4_Tasks(void)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
static void DRV_TMR4_Close(void)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void DRV_TMR2_CounterValueSet(uint32_t value)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
static void Send_Message_Tasks(void)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void DRV_TMR2_CounterClear(void)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
static const uint8_t Xmit11[312]
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
static void Init_WL_CPS(void)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
static void Test_Manchester(void)
uint8_t Calc_CRC_Array(uint16_t Count, const uint8_t Bytes [])
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void qqqbitmapreset(qqnull_params)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
static unsigned char qqqzzglobflag
DRV_USART_LINE_CONTROL_SET_RESULT
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t DRV_PMP0_Read(void)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
static void DRV_TMR0_Open(void)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
DRV_USART_BAUD_SET_RESULT
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void Set_WL_CPS_CurrentLimit(uint8_t value)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
static void Send_Mark(void)
static void qqoutput0(FILEPOINT char *s)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
static void qqqqinitialise(int ii)
static void qqoutput(FILEPOINT char *s, int i)
uint8_t jobQueueReserveSize
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void DRV_IC0_Initialize(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_MODULE_INIT moduleInit
static void Decode_Manchester(void)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
static bool Check_Manchester(void)
void DRV_PMP0_ModeConfig(void)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
static int qqqisinitialised
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
bool send_message_complete_flag
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
void PLIB_USART_Disable(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_CHANNEL_CHAIN_PRIO
static SYS_STATUS DRV_TMR1_Status(void)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void DRV_TMR1_CounterValueSet(uint32_t value)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
INT_SOURCE txInterruptSource
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
static void DRV_TMR0_DeInitialize(void)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
static int fsk_60zscanf(char *qqscan_str)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_Enable(USART_MODULE_ID index)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
bool DRV_USART0_TransmitBufferIsFull(void)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void Generate_Sine_Wave_Data(float32_t NoOfTicks)
static SYS_STATUS DRV_TMR3_Status(void)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
bool DRV_TMR1_Start(void)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void DRV_TMR3_CounterValueSet(uint32_t value)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR1_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
static SYS_STATUS DRV_TMR4_Status(void)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_ADC0_Close(void)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
bool DRV_TMR2_Start(void)
bool spi_write_complete_flag
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void DRV_TMR3_StopInIdleEnable(void)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void DRV_TMR3_CounterClear(void)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
static void MAN_PROCESS_Tasks(void)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void DRV_TMR3_StopInIdleDisable(void)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static SYS_STATUS DRV_TMR0_Status(void)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
uint8_t Get_CRC_Value(void)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
static void qqqupload(qqnull_params)
bool SYS_DMA_IsBusy(void)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
uint16_t DRV_IC0_Capture16BitDataRead(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void DRV_TMR3_Initialize(void)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
uint32_t DRV_TMR0_CounterValueGet(void)
static int fsk_60zqqzqz(qqnull_params)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void DRV_TMR1_Tasks(void)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
DRV_SPI_BUFFER_TYPE bufferType
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_CounterClear(void)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void DRV_TMR_Stop(DRV_HANDLE handle)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
static int qqqqbmselwidth
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void Reset_CRC_Value(void)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
void DRV_TMR1_Initialize(void)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR0_PeriodValueSet(uint32_t value)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void qqqtotalupload(void)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
uint32_t DRV_TMR0_PeriodValueGet(void)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
SPI_FRAME_PULSE_EDGE framePulseEdge
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
static volatile float32_t errorMark
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void DRV_TMR0_CounterValueSet(uint32_t value)
uintptr_t DRV_USART_BUFFER_HANDLE
void(* ldra_void_function)()
void DRV_USART0_Deinitialize(void)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void DRV_TMR1_StopInIdleEnable(void)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void DRV_USART0_Close(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void DRV_TMR0_Initialize(void)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
bool DRV_TMR_Start(DRV_HANDLE handle)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
CLK_BUSES_PERIPHERAL spiClk
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
void APP_Initialize(void)
bool DRV_SPIn_TransmitterBufferIsFull(void)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART0_WriteByte(const uint8_t byte)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
SPI_COMMUNICATION_WIDTH commWidth
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
static void DRV_TMR1_Open(void)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
uint32_t DRV_IC0_Capture32BitDataRead(void)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
static void Init_FSK(void)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void SYS_DEBUG_Print(const char *format,...)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
static void DRV_TMR1_Close(void)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
static int fsk_60zqendz(int qqqi)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
static void DRV_TMR0_Close(void)
static void DRV_TMR2_DeInitialize(void)
static void DRV_TMR2_Open(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void DRV_TMR1_StopInIdleDisable(void)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void DRV_TMR1_DeInitialize(void)
void Set_Bias(uint8_t value)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
bool DRV_SPIn_ReceiverBufferIsFull(void)
static int fsk_60zqzqzq(int qqqi)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
static uint8_t TimeMark[312]
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t DRV_TMR4_PeriodValueGet(void)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void DRV_TMR0_CounterClear(void)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
uint32_t DRV_TMR1_CounterValueGet(void)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void DRV_TMR4_Initialize(void)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool DRV_IC0_BufferIsEmpty(void)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
static void DRV_TMR2_Close(void)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
static void Flush_Buffer_Manchester(void)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
void SYS_PORTS_Initialize()
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
void DRV_TMR4_CounterValueSet(uint32_t value)
void DRV_TMR2_StopInIdleEnable(void)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
uint8_t Calc_CRC_Uplink(uint16_t Count, const uint8_t Bytes [])
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
uintptr_t DRV_USART_BUFFER_HANDLE
uint8_t DRV_USART0_ReadByte(void)
static void Package_Manchester(void)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
static void Read_WL_CPS_V_I(void)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void DRV_TMR0_StopInIdleEnable(void)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
static volatile float32_t errorSpace
static void Send_Space(void)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
uintptr_t DRV_SPI_BUFFER_HANDLE
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
static void DRV_TMR3_Open(void)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_IC_Stop(DRV_HANDLE handle)
SPI_AUDIO_PROTOCOL audioProtocolMode
void SYS_DMA_Resume(void)
void SYS_DMA_Suspend(void)
void DRV_ADC1_Close(void)
void DRV_ADC_Initialize(void)
DRV_SPI_CLOCK_MODE clockMode
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
void DRV_TMR4_StopInIdleDisable(void)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
void DRV_USART_Close(const DRV_HANDLE handle)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void DRV_TMR4_Open(void)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
SYS_ERROR_LEVEL gblErrLvl
static uint8_t TimeSpace[168]
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool DRV_TMR3_Start(void)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
#define DRV_IC_Close(handle)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
static void DRV_TMR3_Tasks(void)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
INT_SOURCE rxInterruptSource
static void Init_Manchester(void)
void DRV_USART0_TasksError(void)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void SYS_DEBUG_Message(const char *message)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
void Adjust_WL_CPS_Voltage(uint8_t target)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
bool DRV_TMR4_Start(void)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void DRV_PMP0_Initialize(void)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
INT_SOURCE errInterruptSource
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void DRV_PMP0_Write(uint8_t data)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void DRV_TMR3_Close(void)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void Calc_Auto_Bias(void)
ldra_void_function qqqaccumreset[QQQnumfil]
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR0_Start(void)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
uint32_t DRV_TMR1_PeriodValueGet(void)
DRV_USART_TRANSFER_STATUS
void Prepare_Dwn_Msg(uint8_t Identifier, uint8_t Cmd, uint8_t Msg_Length)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
struct _DRV_SPI_INIT DRV_SPI_INIT
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
uint32_t DRV_TMR2_CounterValueGet(void)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
uint32_t DRV_TMR4_CounterValueGet(void)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
static void DRV_TMR3_DeInitialize(void)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_SPI_TASK_MODE taskMode
static float32_t Calc_Fsk_Scaling(void)
void DRV_TMR4_StopInIdleEnable(void)
static void DRV_TMR0_Tasks(void)
static const uint8_t Xmit00[168]
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void DRV_TMR_Close(DRV_HANDLE handle)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void DRV_TMR4_PeriodValueSet(uint32_t value)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
SYS_STATUS DRV_USART0_Status(void)
void DRV_TMR3_PeriodValueSet(uint32_t value)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
#define DRV_IC_Open(drvIndex, intent)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
static int qqqstructzzopen
static void Check_WL_CPS_Over_Current(void)
void DRV_ADC_DeInitialize(void)
SPI_FRAME_SYNC_PULSE frameSyncPulse
ldra_void_function qqqaccumupload[QQQnumfil]
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void DRV_USART0_TasksTransmit(void)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void Calc_CRC(uint16_t nbits, uint8_t thebits)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void DRV_TMR2_Initialize(void)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)